1. Field of the Invention
The invention generally relates to computer systems, and more particularly to a system and method of interfacing a highly integrated microprocessor to a secondary level (L2) cache.
2. Description of Related Art
The trend with integrated circuits, particularly microprocessors, is for greater integration of sub-systems onto a single die which were traditionally provided for off-chip. As a consequence, integrated circuit die sizes are increasing--requiring larger packages. Moreover, another consequence of the increased integration is the so-called "pad-width limited" phenomenon wherein the required interconnections between the die and the outside world have increased to a point where package size and peripheral bond pad widths are approaching theoretical limits.
As way of further background, the Peripheral Component Interconnect (PCI) bus is a widely adopted protocol for use as a so-called "local" or "mezzanine" bus to couple external devices, such as, but not limited to, a video display adapter or memory controller, to a central processing unit (CPU) core without interfering with activity on the immediate "CPU bus". Accordingly, ancillary activities can take place substantially simultaneously without inducing much latency into CPU core execution. The PCI-bus protocol is described in, among other places, the PCI Local Bus Specification Rev. 2.0, dated Apr. 30, 1993, by the PCI Special Interest Group, Hillsboro, Oreg., and the Microprocessor Report article entitled Local Buses Poised To Enter PC Mainstream, dated Jul. 8, 1992, by Michael Slater and Mark Thorson, both herein incorporated by reference.
While the local or mezzanine bus such as the PCI bus provides a decoupled, high bandwidth (with respect to an ISA bus) communication channel with the CPU core, its speed has not kept up with the internal speed of the CPU core. This is due, in part, to the somewhat cumbersome protocol required to support a wide range and variety of peripherals. Currently, for example, the PCI-bus is specified for 33 MHz operation while internal CPU core speeds are exceeding 100 MHz. Additionally, the communication channel bandwidth provided by the local or mezzanine bus tends to be utilized in disjointed temporal chunks--leaving large portions unused.
In traditional microprocessor systems designs, the level-two "L2" cache resides external to the CPU core along with external support logic. The L2 cache is typically coupled to the CPU core through the external CPU bus (address, data, and control lines) and is controlled by the external support logic. This type of L2 cache configuration (along with PCI-bus support circuitry) is exemplified in the Microprocessor Report article entitled Intel Unveils First PCI Chip Set, dated Dec. 9, 1992, by Michael Slater, and in the Microprocessor Report article entitled Digital Reveals PCI Chip Sets For Alpha, dated Jul. 12, 1993, by Linley Gwennap. A drawback with this L2 cache configuration is that the CPU bus must be made external--compounding the required number of pins, pad-width limitations, and packaging size limitations.
Another L2 cache configuration is exemplified in the Microprocessor Report article entitled Intel's P6 Uses De-coupled Superscalar Design, dated Feb. 16, 1995, by Linley Gwennap. This configuration employs the so-called Multi-Chip-Module (MCM) wherein two or more separate die are included in one physical package. In the particular case of the P6 microprocessor, the L2 cache resides on a separate die from the CPU core and is coupled together by a dedicated L2 cache bus rather than the CPU bus. A drawback with this configuration is that the L2 cache type and size must be fixed at the time of manufacture of the MCM. Another drawback with this configuration is that the entire MCM must be scrapped if either the L2 cache or the CPU core is defective. Yet another drawback with this configuration is that the dedicated cache bus must be bonded internally within the package between the CPU core and the L2 cache--increasing the package size and cost.
As a way of further background, the PCI Local Bus Specification Rev. 2.0 defines optional cache support pins (SBO# and SDONE) for cacheable memory. This approach however, has at least two limitations. First, the SBO# and SDONE pins are intended only to support cache memory local to a PCI master device on the PCI-bus which typically is separate and disenfranchised from the CPU core. Secondly, adherence to the PCI-bus protocol throttles L2 cache performance.
As a way of yet even further background, integrating a PCI-bus master and support logic into the CPU requires additional die space and more importantly, an addition of a minimum of forty-nine external pins. Consequently, up until now, integrating a PCI-bus and supporting an L2 cache (requiring access to the CPU bus or a dedicated bus) has been impracticable due to pin, pad width, packaging, and cost limitations.
Accordingly, it can be seen that there is a need for a system and method of interfacing an L2 cache to a highly integrated central processing unit employing a local bus without limiting L2 cache performance, while maintaining a general purpose local bus that is compatible with a standard protocol.